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NAMA

vpassert - Preprocess Verilog code assertions

RINGKASAN

vpassert [ --membantu ] [ --tanggal ] [ --diam ] [ -y directories... ] [ file ... ]

DESKRIPSI

Vpassert will read the specified Verilog files and preprocess special PLI assertions. The
files are written to the directory named .vpassert unless another name is given with -o.
If a directory is passed, all files in that directory will be preprocessed.

ARGUMEN

Standard VCS and GCC-like parameters are used to specify the files to be preprocessed:

+libext+I<ext>+I<ext>... Specify extensions to be processed
-f I<file> Parse parameters in file
-v I<file> Parse the library file (I<file>)
-y I<dir> Parse all files in the directory (I<dir>)
-II<dir> Parse all files in the directory (I<dir>)
+incdir+I<dir> Parse all files in the directory (I<dir>)

To prevent recursion and allow reuse of the input.vc being passed to the simulator, if the
output directory is requested to be preprocessed, that directory is simply ignored.

--allfiles
Preprocess and write out files that do not have any macros that need expanding. By
default, files that do not need processing are not written out.

This option may speed up simulator compile times; the file will always be found in the
preprocessed directory, saving the compiler from having to search a large number of -v
directories to find it.

--axiom
Special Axiom ATHDL enables/disables added around unreachable code.

--call-error <function>
When $uerror (or $uassert etc.) wants to display a message, call the specified
function instead of $display and $stop.

--call-info <function>
When $uinfo wants to display a message, call the specified function instead of
$display.

--call-warn <function>
When $uwarn (or $uwarn_clk etc.) wants to display a message, call the specified
function instead of $display and $stop.

--tanggal
Check file dates and sizes versus the last run of vpassert and don't process if the
given source file has not changed.

--mengecualikan
Exclude processing any files which begin with the specified prefix.

--membantu
Menampilkan pesan ini dan versi program dan keluar.

--language <1364-1995|1364-2001|1364-2005|1800-2005|1800-2009|1800-2012>
Tetapkan standar bahasa untuk file. Ini menentukan token mana yang merupakan sinyal
versus kata kunci, seperti "lakukan" yang selalu umum (sinyal keluaran data, versus loop do-while
kata kunci).

--minimum
Include `__message_minimum in the $uinfo test, so that by defining __message_minimum=1
some uinfos may be optimized away at compile time.

--nolin
Do not emit `line directives. If not specified they will be used under --language
1364-2001 and later.

--nopli
Delete all 'simple' PLI calls. PLI function calls inside parenthesis will not be
changed, and thus may still need to be manually ifdef'ed out. Useful for reducing the
amount of `ifdef's required to feed non-PLI competent synthesis programs.

--tidak berhenti
By default, $error and $warn insert a $stop statement. With --nostop, this is
replaced by incrementing a variable, which may then be used to conditionally halt
simulasi.

--Hai fillet
Use the given filename for output instead of the input name .vpassert. If the name
ends in a / it is used as a output directory with the default name.

--diam
Suppress messages about what files are being preprocessed.

--realintent
Special RealIntent enable/disables added around unreachable code.

--synthcov
When "ifdef SYNTHESIS" is seen, disable coverage. Resume on the `else or `endif.
This does NOT follow child defines, for example:

`ifdef SYNTHSIS
`define MYSYNTH
`endif
`ifdef MYSYNTH // This will not be coveraged-off

--timeformat-units unit
If specified, include Verilog $timeformat calls before all messages. Use the provided
argument as the units. Units is in powers of 10, so -9 indicates to use nanoseconds.

--timeformat-precision sebelum
When using --timeformat-units, use this as the precision value, the number of digits
after the decimal point. Defaults to zero.

--vericov
Special Vericov enable/disables added around unreachable code.

--verilator
Special Verilator translations enabled.

--Versi: kapan
Menampilkan versi program dan keluar.

--vcs
Special Synopsys VCS enables/disables added around unreachable code.

FUNGSI

These Verilog pseudo-pli calls are expanded:

/*vp_coverage_off*/
Disable coverage for all tools starting at this point. Does not need to be on a
unique line.

/*vp_coverage_on*/
Re-enable coverage after a vp_coverage_off. Does not need to be on a unique line.

$uassert (kasus, "message", [vars...] )
Report a $uerror if the given case is FALSE. (Like menegaskan() in C.)

$uassert_amone (sig, [sig...], "message", [vars...] )
Report a $uerror if more than one signal is asserted, or any are X. (None asserted is
ok.) The error message will include a binary display of the signal values.

$uassert_info (kasus, "message", [vars...] )
Report a $uinfo if the given case is FALSE. (Like menegaskan() in C.)

$uassert_onehot (sig, [sig...], "message", [vars...] )
Report a $uerror if other than one signal is asserted, or any are X. The error
message will include a binary display of the signal values.

$uassert_req_ack (req_sig, ack_sig, [data_sig,...] )
Check for a single cycle request pulse, followed by a single cycle acknowledgment
pulse. Do not allow any of the data signals to change between the request and
pengakuan.

$ucheck_ilevel (tingkat )
Return true if the __message level is greater or equal to the given level, and that
global messages are turned on.

$ucover_clk (jam, label)
Similar to $uerror_clk, add a SystemVerilog assertion at the next specified clock's
edge, with the label specified. This allows cover properties to be specified "inline"
with normal RTL code.

$ucover_foreach_clk (jam, label, "msb:lsb", (... $ui ...))
Similar to $ucover_clk, however cover a range where $ui in the expression is replaced
with the range index.

Range is "msb:lsb" to indicate from msb ke bawah lsb inclusive, and/or a comma separated
list of values.

Mirip dengan:

for ($ui=msb; $ui>=lsb; $ui=$ui-1) begin
if (expression with $ui)
$ucover_clk(clock, label ## "_" ## bit)
akhir

However there's no way to form a label from a for loop (as psudocoded with ## above),
thus this macro.

$ui Loop index used inside $ucover_foreach_clk.

$uinfo (tingkat, "message", [vars...] )
Report a informational message in standard form. End test if warning limit exceeded.

$uerror ("message", [vars...] )
Report a error message in standard form. End test if error limit exceeded.

$uerror_clk (jam, "message", [vars...] )
Report a error message in standard form at the next clock edge. If you place a
$uerror etc in a combo logic block (always @*), event based simulators may misfire the
assertion due to glitches. $uerror_clk fixes this by instead creating a temporary
signal and then moving the assert itself to a new clocked block at the specified edge.
Note any variables printed will be the values at the time of the next clock edge,
which may differ from the value where the $uerror_clk is assigned.

$uwarn ("message", [vars...] )
Report a warning message in standard form.

$uwarn_clk (jam "message", [vars...] )
Report a warning message in standard form at the next clock edge. See $uerror_clk.

DISTRIBUSI

Verilog-Perl adalah bagian darihttp://www.veripool.org/> alat perangkat lunak Verilog EDA gratis
rangkaian. Versi terbaru tersedia dari CPAN dan dari
<http://www.veripool.org/verilog-perl>.

Hak Cipta 2000-2016 oleh Wilson Snyder. Paket ini adalah perangkat lunak gratis; Anda dapat mendistribusikan kembali
itu dan/atau memodifikasinya di bawah persyaratan Lisensi Publik Umum GNU
Versi 3 atau Lisensi Artistik Perl Versi 2.0.

PENULIS

Wilson Snyder[email dilindungi]>, Duane Galbi <[email dilindungi]>

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