This is the Linux app named SmGen whose latest release can be downloaded as smgen_0.91.tgz. It can be run online in the free hosting provider OnWorks for workstations.
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SmGen
DESCRIPTION:
SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing
Audience
Science/Research, Developers, Engineering
User interface
Command-line
Programming Language
Perl, VHDL/Verilog
Categories
This is an application that can also be fetched from https://sourceforge.net/projects/smgenerator/. It has been hosted in OnWorks in order to be run online in an easiest way from one of our free Operative Systems.